See moreThe XGMII interface, specified by IEEE 802. Interfaces. PCS Transmit Process! Transmit channel in normal mode:! Blocks generated continuously based upon TXD<31:0> and TXC<3:0> signals on XGMII! 66 bit blocks are packed by gearbox into 16 bit data units and sent to PMA or WIS viaRGMII is a 12-pin interface, while SGMII can operate as either a four- or six-pin interface. Connection to the SerDes is through a configu-rable 16-, 20-, 32-, 40-, or 64-bit interface. SerDes TX RX MII Serial Figure 5–1. PHY x. PCS. The standard XLGMII or CGMII implementation consists of 32 bit wide data bus. Register Access Definition 8. We just have to enable FLOW CONTROL on our MAC side. 25MHz? I'm currently reading the IEEE XGMII specification (IEEE Std 802. 3-2008 specification. supports bi-directional data flow and can be deployed multiple ways: • Interface Conversion: Connect data steams between flight units using XAUI and test systems using 10GigE. 3bz Task Force – Pittsburg, PA May 2015 5 • 10G XGMII (Clause 46) - Logical o 32-bit DDR TXD, 4-bit TXC and TX_CLK o 32-bit DDR RXD, 4-bit RXC and RX_CLK XGXS (Clause 47) – XAUI Electrical Spec (PMA) o 4 SERDES TX and 4 SERDES RX (PCS 8B/10B) @ 3. The BCM84885 supports the USXGMII, XFI, 5000BASE-X, 2500BASE-X, and 1000BASE-X (SGMII) interface for connection to a MAC. 3bm Annexes 83D and 83E 5I would retain the current MDC/MDIO electrical specification. NOTE: BRCM had a PHY but is changed speeds internally from 10. All transmit data and control. So I don't think there's an easy way to connect 100G and 25G. The interface between the PCS and the RS is the XGMII as specified in Clause 46. The 5GBASE-R PCS provides all services required by the XGMII including Encoding (decoding) of XGMII data octets to (from) 64B/66B blocks for communication with the underlying PMA. Optional 802. to the PCS synchronization specification. 3 Clause 46 ratified specification enabling a variety of PHY and MAC chips. 25 MHz interface clock. > 3. 3 10 Gbps Ethernet standard. 1. Low Latency Ethernet 10G MAC 8. Table 1. All forum topics; Previous Topic; Next Topic; 4 Replies 4. 3z Interim, January 1997The MDI interface to copper cable is always a media interface. For D1. Link to this page:2. 0 > 2. ) • 1. According to IEEE802. This is the SDS (Start of Data Stream). Design Example MAC Variant PHY Development Kit 10GBase-R Ethernet 10G Native PHY Intel Arria 10 GX Transceiver SI. The specifications and information herein are subject to change without notice. AUTOSAR Interface. 8. 3ae Clause 22 and Clause 45 Compliant Management Data Input / Output Interface Modes (Either 1. 3125. The PCS service interface is the XGMII, which is defined in Clause 46 running at 5Gb/s. Uses 7 series, Virtex 6, Virtex 5, Virtex 4, and Spartan 6 transceivers running 4 lanes at 3. XGMII Data Interface Signals XGTMIICLK Output XGMII Transmit Clock (156. Introduction. al [11] establish a . Previous definition/implementations cover single (SGMII) and quad (QSGMII) options. Status Signals. 2 XAPP606 (v1. With experience of SSTL, I believe we can define the HSTL interface in more reasonable time frame. Once you see an SDS, it means that the exchange of ordered sets has finished. - Wishbone Interface for control. Software Architecture – AUTOSAR Defined Interfaces. GMII Electrical Interface Specification Merge the MII electrical specifications in terms of input and output buffer strengths, TTL Level signalling and compatibility with 5V and 3. The IP core is compatible with the RGMII specification v2. Because of this,. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. The 10GBASE-X PCS provides all services required by the XGMII and in support of the 10GBASE-X PMA, including:Definitely not XGMII (32-bit DDR, was never really seen off-chip) or XAUI (4 lanes of 3. Mark as New; Bookmark; Subscribe; Mute; Subscribe to RSS Feed;The interface between the PCS and the RS is the XGMII as specified in Clause 46. Operating Speed and Status Signals. 5G, 5G, or 10GE data rates over a 10. This page contains resource utilization data for several configurations of this IP core. In the 10G Ethernet segment, the Universal Serial 10G Media Independent Interface (USXGMII) IP core from Microchip enables building 10GBASE-R solutions on PolarFire. Hello everyone, I am searching for a chip that connects to QuadSGMII on one side and multiple SGMII on the other. Core10GMAC is configured for XGMII mode with a core data width of 64 bits. Abstract: 88X2040-BAN xGMII to rj45 phy marvell IEEE 946 motherboard Text: packets through the XAUI PCS soft IP and the LatticeECP3 XAUI PCS to the Marvell 88X2040 device. A Makefile controls the simulation of the. Medium. Being media independent means that different types of PHY devices for connecting to different media can be used. The system data width, that is, the width of the interface to the user logic, is c onfigured as 64 bits. 6. 2) enabled TX and RX bit in TX_ctrl and Rxctrl registers . With the inclusion of the XAUI interface, the 10 GMAC core can now support 10. 3125 Gbps/32-bit = 322. 1. Between the MAC and the PHY is the XGMII, or 10 Gigabit Media Independent Interface. 16. 5. 1. The Reduced Gigabit Media Independent Interface (RGMII) module provides an RGMII interface to an existing Ethernet MAC design with a GMII or TBI interface, for example the Gigabit Ethernet MAC (GEM) available from Cadence Design Foundry. The test parameters include the part information and the core-specific configuration parameters. To use custom preamble, set the tx_preamble_control register to 1. Both media access control (MAC) and physical coding sublayer/physical medium attachment (PCS/PMA) functions are included. XLGMII is for 40G Interface. The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802. This block. normal signal, the XGMII input is ignored until PCS_Test. Unidirectional. We are using the 10G/25G Ethernet Subsystem for 10G with PCS only. XGMII. The XgmiiSink receives XGMII traffic, including monitoring internal interfaces. Each direction is independent and contains a 32-bit data path, as well as clock and control signals. com URL: design-gateway. . 1. 125GBaud/s PCS = Physical Coding Sublayer PMA = Physical Medium Attachment PMD = Physical Medium Dependent (not for all PHYs) XFI XFI (Not specified in IEEE Std 802. Please refer to PG210. • No internal interface is super-rated, • XGMII rate is preserved (312. 5. specification for internal use only. Fair and Open Competition. Avalon® Memory-Mapped Interface Signals 6. XAUI is standardized instantiation of XGMII Extender (Clause 47) In practical implementations physical interface between MAC and PHY XSBI is an optional physical instantiation of PMA service interface for 10GBASE-R and 10GBASE-W (Clause 51) 16-bit bidirectional interface with source synchronous clock 10-Gbps Ethernet MAC MegaCore Function user guide ›. 5 volts per EIA/JESD8-6 and select from the options > within that specification. Simulation and verification. The primary. This is most critical for high density switches and PHY. The IP supports 64-bit wide data path interface only. 3 Clause 46, is the main access to the 10G Ethernet physical layer. 125 Gbps) or XFI (1x10. 7. 1. Rockchip RK3588 datasheet. AVST-XGMII – monitor the packet condition at client Avalon-ST and XGMII interface a. VIP Options. XFI and SFI electrical specifications respectively apply to XFP and SFP+ system front port optical modules. 3-2008 specification requires each 10GBASE-R link to support a 10 Gbps data rate at the XGMII interface and a 10. transceiver interface. The RGMII interface has been designed in accordance with the standards and specifications agreed in theThe CoaXPress-over-Fiber Bridge IP Core allows to connect a CoaXPress IP Core to an XGMII (10 Gbps Media Independent Interface) bus inside an FPGA. You are required to use an external PHY device to. 1for definition of SoS architectures lies in interface specification and a . 5. CAUTION: The implemented D-PHY resistor values need to be adjusted based on user design. > > 1. The SERDES circuitry is configured to support source synchronous and asynchronous serial data communication for the SGMII interface at 1. 8V devices whose MDC/MDIO ports can withstand this without blowing a hole in the oxide. 3. It really isn't right for the technologies we will be using for these chips. 1 of the IEEE P802. Uses device-specific transceivers for the RXAUI interface. 3 to add 100 Mb/s Physical Layer specifications and. 5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Updated for Intel ® Quartus Prime Design Suite: 19. 3. Supports 10M, 100M, 1G, 2. Designed to Dune Networks RXAUI specification. 5000BASE-X, 2500BASE-X, and 1000BASE-X (SGMII) interface for connection to a MAC. 3125Gbps to. RGMII uses four-bit wide transmit and receive datapaths, each with its own source synchronous clock. Reference industry standard electrical specifications Interface Locations Management 32 data bits, 4 control bits, one clock, for transmit 32 data bits, 4 control bits, one clock, for receive Dual Data Rate (DDR) signaling, with data and control driven and sampled on both rising edge and falling edge of clock Clock Control Data[A/B] Data[A] Data[B] Host Interface Speed Data width # Pins Clock Frequency Transmission Specification QSGMII 4x ≤1. Georg Pauwen. The waveform below shows a DLLP packet. 3. 3 is silent in this respect for 2. 25 Gbps line rate to achieve 10-Gbps data rate. So to test initially I taken Example design of PCS/PMA IP and there I altered 1) ctl_loopback bit 1-> 0 (not setting in loop back) . The Intel® Stratix® 10 devices contain a combination of GX, GXT, or GXE channels, in addition to the. 3u and connects different types of PHYs to MACs. 5 Gb/s and 5 Gb/s XGMII operation. Designed to meet the USXGMII specification EDCS-1467841 revision 1. 3 Ethernet standard, physical layer (PHY) provides media-independent interface (MII) to the media access control (MAC) layer, which is 10G media-independent interface (XGMII) in 10G Ethernet and 40G media-independent interface (XLGMII) in 40G Ethernet []. 14. XGMII interface in my view will be short lived. 15Introduction. 1. XGMII Interface 10G 32-bit MODE(MAC+ $;, /LWH :UDSSHU SERDES DATA MUX. The 10 Gigabit Media Independent Interface ( XGMII) is an interface standard that uses 72 data pins for both RX and TX. This revision offers architecture diagram of Non-RT RIC, collects requirements on the Non-RT RIC framework, Non-RT RIC logical functions and services of the R1 interface. It can also be used as a serial communication bus between the PowerQUICC™ MPC8313E and other peripherals such as through a. version string. The data are multiplexing to 4 lanes in the physical layer. The SERDES interface can be either a MAC interface or a media interface. It can also be configured to be compliant with the 1000Base-X 1Gbps Ethernet Specification (Auto-Negotiation not supported). USXGMII - Multiple Network ports over a Single SERDES. Performance and Resource. ECU-Hardware. There are a total of 28 pins within a cluster, so each cluster has enough signals to implement one GMII interface. I see three alternatives that would allow us to go forward to > TF ballot. Small Form-factor Pluggable (SFP) is a compact, hot-pluggable network interface module format used for both telecommunication and data communications applications. Reconciliation Sublayer (RS) and XGMII. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and. 1. The XGMII design is now provided with the 10-Gig MAC Core in CORE Generator. When TCP/IP network is applied in. 3 Ethernet standard, physical layer (PHY) provides media-independent interface (MII) to the media access control (MAC) layer, which is 10G media-independent interface (XGMII) in 10G Ethernet and 40G media-independent interface (XLGMII) in 40G Ethernet []. Statement on Forced Labor. 3125 Gbps のシリアル シングル チャネルの PHY をインプリメントして、XFI 電気的仕様を使用した XFP への直接接続や、SFI 電気的仕様を使用した SFP+ オプティカル. 1: XGMII (Clause 46) - Logical o 32-bit DDR TXD, 4-bit TXC and TX_CLK o 32-bit DDR RXD, 4-bit RXC and RX_CLK XGXS (Clause 47) – XAUI Electrical Spec (PMA) o 4 SERDES TX and 4 SERDES RX (PCS 8B/10B) @ 3. 3, Clause 47. XGMII signaling is based on the HSTL class 1 single-ended I/O standard, which. interface. The XgmiiSink receives XGMII traffic, including monitoring internal interfaces. The 10 Gigabit Media Independent Interface (XGMII) is an interface standard that uses 72 data pins for both RX and TX. WishBone compliant: Yes. Supports 10-Gigabit Fibre Channel (10-GFC. 1. The name is a concatenation of the Roman numeral X, meaning ten, and the initials of. The 10GBASE-R PHY with IEEE 1588v2 uses both the TX Core FIFO and the RX Core. This project will specify additions to and appropriate modifications of IEEE Std 802. Arria V transceivers and soft PCS solution in a XAUI configuration do not support the XGMII interface to the MAC/RS as defined in IEEE 802. xgmii mdi up to 10 gbps clt – coax line terminal cnu – coax network unit mdi – medium dependent interface oam – operations, administration, & maintenance pcs – physical coding sublayer phy – physical layer device pma – physical medium attachment pmd – physical medium dependent xgmii – gigabit media independent interfaceFor D1. DisplayPort (DP) is a digital display interface developed by a consortium of PC and chip manufacturers and standardized by the Video Electronics Standards Association (VESA). 1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. We are using the Yocto Linux SDK. The 10GEMAC core is designed to the IEEE 802. What i want to do is i want to feed the PCS with xgmii_tx signals, connect the txn/txp to rxn/rxp respectively and monitor the xgmii_rx signals whether they are the same as xgmii_tx. Network. 4 11/18 Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100Support to extend the IEEE 802. But HSTL has more usage for high speed interface than just XGMII. . Unlike previous Ethernet. 3ba standard. Also, take a look at the timing diagrams in figures 46-5 and 46-6 on page 451 of IEEE. The RGMII interface has been designed in accordance with the standards and specifications agreed in theThe present clauses in 802. 3ae 10 Gigabit Ethernet Summary n The XGMII coding proposal is stable n The EIA/JEDEC SSTL_2 standard can be referenced for the XGMII electrical specification n The timing proposal presented herein is a starting point for further discussion 10-gigabit media-independent interface (XGMII) The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. It differs from GMII by its low-power and low pin count serial interface (commonly referred to as a SerDes ). PCS Registers 5. 3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface XGMII. Release Information 1. The XGMII interface, specified by IEEE 802. 5Gb/s 8B/10B encoded - 3. The generic nature of this interface facilitates mapping the CoaXPress signaling into the. speed XGMII Attachment Unit Interface (XAUI) to transmit or receive data. AXI4-Lite $;, &URVVEDU ,3 AXI4-Lite 1G Ethernet GMII Interface PCS IP /LQH 5DWH 6ZLWFKLQJ /RJLF. Simulation and verification. Field Name Type Description; openapi: string: REQUIRED. 4. 3 is used as the interface between an Ethernet physical layer device and a media access controller. XGMII Signals 6. 18. 1 Throughput 11 2. 5 Gb/s and 5 Gb/s XGMII operation. 145 400 Gb/s Attachment Unit Interface (400GAUI-n): A physical instantiation of the PMA service interface to extend the connection between 400 Gb/s capable PMAs over n lanes, used for chip-to-chip or chip-to-module interconnections. 3bz-2016 amending the XGMII specification to support operation at 2. Media Independent Interface ( MII )，介质独立接口，起初是定义100M以太网（Fast Ethernet）的 MAC 层与 PHY 芯片之间的传输标准（802. RGMII uses four-bit wide transmit and receive datapaths, each with its own source synchronous clock. 因此XFP模块尺寸比较大，功耗也比较大，这个对于需要多端口高密度的系统，比如数通交换机会. This specification defines USGMII. 3125 Gbps serial line rate with 64B/66B encoding 10GBASE-KR and 1000BASE-KX is the electrical backplane physical layer implementation for the 10 Gigabit and 1 Gigabit Ethernet link defined in clause 72 and clause 70. The BCM84885 is a highly integrated solution combining digital adaptive equalizers, ADCs, phase-locked loops, line drivers, encoders, decoders, echo cancelers, crosstalk cancelers, and all required support circuitry. Close Filter Modal. XGMII Transmission 4. XGMIIはMACとPHYの間に位置する。RSはMACのビットシリアルプロトコルをPHYのパラレルエンコーディングに適合させる。 XGMIIの使用は必須ではないが、PCSはXGMIIを想定して仕様が定義されて. The generic nature of this interface facilitates mapping the CoaXPress signaling into the. 4. 7. USGMII provides flexibility to add new features while maintaining backward compatibility. 6. MAC control. Hardware and Software Requirements. Its work covers 2G/3G/4G/5G. : info: Info Object: REQUIRED. The Universal Serial Gigabit Media Independent Interface (USGMII) is an extension of the current SGMII and QSGMII. This module converts XGMII interface of XGMAC core to high speed serial interface needed by physical interface. Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). 0. 3. The PHY IP core can be used with either Intel® FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156. The MAC core along with FIFO-core and SPI4/AXI-DMA engines VMDS-10298. The 10G Ethernet Verification IP is compliant with IEEE 802. 25 Mbps. 3az standard for Energy Efficient Ethernet. XAUI interoperability is based on the 10-Gigabit Ethernet standard (IEEE Standard 802. 25 Gbps). USGMII supports eight 10M/100M/1G network ports over 10Gbps SERDES between MAC and PHY. 2. Position is labelled "nB" where "n" stands for slot# , seeDisplayPort connector A DisplayPort port (top right) near an Ethernet port and a USB port. 1. Intel® Stratix® 10 devices offer up to 144 transceivers with integrated advanced high-speed analog signal conditioning and clock data recovery circuits for chip-to-chip, chip-to-module, and backplane applications. 5Gbps Ethernet core. 3-2008 standard and provides an interface between AHB/AXI Bus and the 10 Gigabit Media Independent Interface (XGMII) using a powerful 64-bit Scatter Gather DMA. However, the Altera implementation uses a wider bus interface in connecting a. 1. 2 Scope : This document describes messages transmitted. Intel PRO/1000 GT PCI network interface controller. The modules are capable of operating with XGMII interface widths of 32 or 64 bits. 3-2012 specification and supports the high-bandwidth demands of network Internet Protocol. 11/13/2007 IEEE 802. 25MHz. I see three alternatives that would allow us to go forward to > TF ballot. 125Gbps 10GBASE-R Clause 49 (IEEE 64B/66B PCS only) o No IEEE Electrical Spec (no PMA) IEEE Specifications • 3. 3ae-2002 specification requires the XAUI PHY link to support a 10 Gbps data rate at the XGMII interface and four lanes each at 3. 4. 3 is silent in this respect for 2. 3-2008 and the IEEE802. The following features are supported in the 64b6xb: Fabric width is selectable. we should see DLLP packets on the interface. XFI和SFI的来源. Resource Utilization 3. XFP光模块标准定义于2002年左右，其内部的收和发方向都带有CDR电路。. Includes MAC modules for gigabit and 10G, a 10G PCS/PMA PHY module, and a 10G combination. 3ae specification defines two PHY types: the LAN PHY and the WAN PHY. 2 V or 2. 3 are described in terms of two primary interfaces Medium dependent interface (MDI) Media independent interface (MII) While the MDI is visible to the user, and usually tightly specified, the MII is often used simply as a convenient way to partition the physical layer specifications from the10 ギガビット イーサネット PCS/PMA (10GBASE-R) は、10 ギガビット イーサネット MAC への接続に XGMII インターフェイスを提供し、10. XAUI addresses several physical limitations of the XGMII. In this demo, the FiFo_wrapper_top module provides this interface. 3 layer diagram 100Mb/s and above RS. 10G/25G Ethernet (PCS only) RX_MII alignment. 0 Cards use the UHS-II bus interface, which features two rows of pins rather than the single row found in UHS-I. we should see DLLP packets on the interface. • Data Capture: Record data packets in-line between twoThe present clauses in 802. The waveform below shows a DLLP packet. The 10GBASE-X PCS provides services to the XGMII in a manner analogous to how the 1000BASE-X PCS provides services to the 1000 Mb/s GMII. XFI and SFI electrical specifications respectively apply to XFP and SFP+ system front port optical modules. 4. This configurable core provides the complete Media Access Control (MAC) and Physical (PHY) layer when used with a transceiver interface. 5x faster (modified) 2. I have however been just a functional person and just a technical person. 3-2008, defines the 32-bit data and 4-bit wide control character. There needs to be some way to allow alternate voltages for this interface and still be standards compliant. MDI. • The TX state machines needs a check to prevent this from happening. Figure 3: 10GBASE-X PHY Structure. 3125 Gbit/s) • Data throughput is reduced: • inter-frame gaps are increased through extended operation of MPCP, which accounts for FEC parity insertion • Extra IDLEs are deleted in PCS and used to insert FEC partiyLow Power FPGAs. Return to the SSTL specifications of Draft 1. Reference HSTL at 1. 6. Several Physical Coding Sublayers known as 10GBASE-X, 10GBASE-R, and10GBASE-W are specified, as well as significant additional supporting material for a 10 GigabitMedia Independent Interface (XGMII), a 10 Gigabit Attachment. This is most critical for high density. Transport. This interface specification is subject to modification and revision to incorporate changes, improvements, and enhancements. 14. 3-2008, defines the 32-bit data and 4-bit wide control character. Introduction. 1. XAUI. If anybody is interested to see this document please go to FC web site at and search for doc 99-251v3. The CoaXPress-over-Fiber Bridge IP Core allows to connect a CoaXPress IP Core to an XGMII (10 Gbps Media Independent Interface) bus inside an FPGA. 2. to the PCS synchronization specification. 2. Core10GMAC is configured for XGMII mode with a core data width of 64 bits. XGMII stands for X (roman 10)- G-M edia- I ndependant- I nterface which is IEEE 802. 1G/2. 3125 Gb/s link. The Ethernet MAC IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping. 25MHz PCS layer XGMII interface implemented as 64-bit (single data rate) SDR interface at 156. 3-2008, defines the 32-bit data and 4-bit wide control character. Features 2. Received Ethernet bytes are available on the 64-bit XGMII interface (RX_MII_D/C). Check MAC PHY XGMII interface signals, no data sent out from MAC. You are required to use an external PHY device to. The present clauses in 802. "JUST" <smile>. Similarly, the XGMII bus corresponds to 10 Gigabit network. > 3. 4. 4. 3125 Gbps serial single channel PHY over a backplane. The columns are divided into test parameters and results. 0 Helpful Reply. USXGMII (Universal Serial 10GE Media Independent Interface) IP コアは、IEEE 802. 1 I inserted an editors note under an "Electrical interface" section as a place holder for an interface to be approved by the Task Force. By default, the MAC TX inserts 7-byte preamble, 1-byte SFD and 1-byte EFD (0xFD) into frames received from the client. Inter-Packet Gap Generation and Insertion 4. Uses 7 series, Virtex 6, Virtex 5, Virtex 4, and Spartan 6 transceivers running 4 lanes at 3. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User GuideIP is needed to interface the Transceiver with the XGMII compliant MAC. These specs were defined by the SFF MSA industry group. 6 Functional block diagraminterface. Introduction to Intel® FPGA IP. The name is a concatenation of the Roman numeral X, meaning ten, and the initials of. XGMII stands for X(roman 10)-G-Media-Independant-Interface which is IEEE 802. These specs were defined by the SFF MSA industry group. 1G/2. The data are multiplexing to 4 lanes in the physical layer. 6. There needs to be some way to allow alternate voltages for this interface and still be standards compliant. If anybody is interested to see this document please go to FC web site at and search for doc 99-251v3. 1 of the IEEE P802. 6. RGMII to GMII converter provides the interface between a standard gigabit media independent interface (GMII) to RGMII conversion. There needs to be some way to allow alternate voltages for this interface and still be standards compliant. Reduced Gigabit Media Independent Interface (RGMII) (Reduced GMII) is the most common interface as it supports 10 Mbps, 100 Mbps, and 1000 Mbps connection speeds at the PHY layer. 32 Gbps over a copper or optical media interface. MDI – Media dependant interface. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 4. nsc. 2 PCIE Interface 9 2 PRODUCT SPECIFICATIONS 10 2. 3ab standard. 4. By offering a standard, hot swappable electrical interface, a single gigabit port can support a wide range of physical media, from copper to long-wave single-mode optical fiber, at. 1G/10GbE PHY Register Definitions 5.